FIG. 1 shows a bidirectional amplifier which includes amplifiers 1 and 2 and pass transistors P.sub.1 and P.sub.2. A pass transistor is a transistor whose function is to either transmit (i.e. "pass") or block a received signal as determined by the application of a control voltage to the gate of the pass transistor. A pass transistor may be either an N channel enhancement mode transistor or a P channel enhancement mode transistor. (Throughout this specification a pass transistor will be represented by the symbol used for P.sub.1 in FIG. 1.) The bidirectional amplifier of FIG. 1 is described in copending U.S. patent application Ser. No. 588,478, which is incorporated herein by reference.
Assuming pass transistors P.sub.1 and P.sub.2 in FIG. 1 are N channel enhancement mode transistors, pass transistor P.sub.1 is on and pass transistor P.sub.2 is off when the control signal Q is high (logical 1) and control signal Q is low (logical 0). The signal on node B is then buffered by amplifier 1, whose output signal is passed by pass transistor P.sub.1 to node A. On the other hand, when Q is low and Q is high, N channel pass transistor P.sub.1 is off, N channel pass transistor P.sub.2 is on, and the signal on node A is buffered by buffer amplifier 2, whose output signal is passed by pass transistor P.sub.2 to node B.
The bidirectional amplifier shown in FIG. 1 has particular utility in a configurable logic array. The term configurable logic array is explained in the detailed description below. At this point it is sufficient to note that in routing signals through various interconnections between configurable logic elements in a configurable logic array, the signal may be weakened or degraded by passing through a large number of pass transistors or CMOS transmission gates. A CMOS transmission gate is illustrated in FIG. 7. An input signal on lead 10-1 passes through N channel transistor 10-4 and P channel transistor 10-5 to output lead 10-2 when a high voltage control signal is applied to control lead 10-3, which is connected to the gate of N channel transistor 10-4 and by means of inverter 10-6 to the gate of P channel transistor 10-5. Conversely, when a low control signal (0 volts) is applied to control lead 10-3, the input signal on lead 10-1 is blocked. Since a signal in a configurable logic array may pass through several CMOS transmission gates or pass transistors each of which attenuates the signal, it is often necessary to amplify or reconstruct the signal by means of a buffer amplifier. The amplifier employed is bidirectional since it is not known when the amplifier is installed in the configurable logic array which way the signal will flow, when the array is ultimately configured.
The bidirectional amplifier of FIG. 1 has the drawback that two buffer amplifiers are required for its implementation. In contrast, the bidirectional amplifier of the present invention uses a single amplifier, thus reducing the cost of implementing a bidirectional amplifier.